A type of commercially available flash memory product is a MirrorBit® memory device available from Spansion, LLC, located in Sunnyvale, Calif. A MirrorBit cell effectively doubles the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit within a cell can be programmed with a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.
A portion of an exemplary MirrorBit® memory device 10, illustrated in FIG. 1, includes a P-type semiconductor substrate 12 within which are formed spaced-apart source/drain regions 14, 16 respectively (both typically having N-type conductivity), otherwise known as bitline regions or bitlines. A charge trapping layer or stack 18 is disposed on the top surface of the substrate between the bitlines. The charge trapping stack 18 typically comprises, for example, a charge trapping layer, often a silicon nitride layer 20, disposed between a first or bottom silicon dioxide layer (commonly referred to as a tunnel oxide layer) 22 and a second or top silicon dioxide layer 24. A gate electrode 26, which typically comprises an N or N+ polycrystalline silicon layer, is formed over the charge trapping stack. An isolation region 40 divides the charge trapping stack below each gate electrode 26 to form a first storage element or bit 28 and a complementary second storage element or bit 30 of memory cells 32 and 34.
Dual bit memory cell 34 is programmed utilizing a hot electron injection technique. More specifically, programming of the first bit 28 of memory cell 34 comprises injecting electrons into the charge trapping layer 20 and applying a bias between bitlines 14 and 16 while applying a high voltage to the control gate 26. In an exemplary embodiment, this may be accomplished by grounding bitline 16 and applying approximately 5 V to bitline 14 and approximately 10 V to the control gate 26. The voltage on the control gate 26 inverts a channel region 36 while the bias accelerates electrons from bitline 14 into the channel region 36 towards bitline 16. The 4.5 eV to 5 eV kinetic energy gain of the electrons is more than sufficient to surmount the 3.1 eV to 3.5 eV energy barrier at channel region 36/tunnel oxide layer 22 interface and, while the electrons are accelerated towards source/drain region 16, the field caused by the high voltage on control gate 26 redirects the electrons towards the charge trapping layer 20 of first bit 28. Those electrons that cross the interface into the charge trapping layer remain trapped for later reading.
Similarly, programming the second bit 30 by hot electron injection into the charge trapping layer 20 comprises applying a bias between bitlines 16 and 14 while applying a high voltage to the control gate 26. This may be accomplished by grounding bitline 14 and applying approximately 5V to bitline 16 and approximately 10 V to the control gate 26. The voltage on the control gate 26 inverts the channel region 36 while the bias accelerates electrons from bitline 16 into the channel region 36 towards bitline 14. The field caused by the high voltage on control gate 26 redirects the electrons towards the charge trapping layer 20 of second bit 30. Those electrons that cross the interface into charge trapping layer 20 of second bit 30 remain trapped for later reading.
As devices densities increase and product dimensions decrease, it is desirable to reduce the size of the various structures and features associated with individual memory cells, sometimes referred to as scaling. However, the fabrication techniques used to produce flash memory arrays limit or inhibit the designer's ability to reduce device dimensions. For example, with 65 nm node devices, it is not necessary to isolate portions of the charge trapping layer of complimentary bits, that is, isolation regions 40 in cells 32 and 34 are not necessary. However, as device dimensions decrease to 45 nm nodes, isolation of the charge trapping layer portions of the complimentary cells by isolation regions 40 becomes advantageous. A convenient method for forming memory device 10 with isolation regions 40 includes forming bitline regions 14 and 16 before forming the gate stacks of cells 32 and 34. However, subsequent high temperature processes such as, for example, thermal oxidation formation or high temperature oxide (HTO) deposition, have a tendency to result in lateral diffusion of the implanted ions of the bitlines. Such diffusion may result in interference between the adjacent bitlines and, hence, degradation of device performance.
Accordingly, it is desirable to provide methods of fabricating dual bit memory devices that permit formation of the bitline regions after formation of the gate stacks, thus minimizing or reducing bitline implant diffusion during manufacture. In addition, it is desirable to provide methods of fabricating flash memory devices that provide better device performance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.